In the manufacture of semiconductor integrated circuits the yield (the ratio of good chips on a wafer to the total number of chips available on a wafer) is determined, among other things, by the density of defects in the wafer and the ability of the circuit design and manufacturing process to compensate for defects. As the chip size is increased the probability of a defect occurring on the chip increases; hence, the number of defects per unit area limits the physical size of the integrated circuit that can be manufactured without defects.
The problems associated with obtaining defect-free semiconductor chips are magnified many times when a single circuit is to be fabricated on an entire wafer.
To date a wafer sized circuit with zero manufacturing defects has not been achieved. Thus integrated circuit manufacturers are forced to employ special techniques to compensate for defects. In chip sized memories, manufacturers commonly add redundant rows and columns of memory and logic elements which can be substituted for defective elements, with overhead circuitry for use after testing the unit to substitute the redundant memory and logic elements. These redundancy techniques are not acceptable for wafer-size integrated circuits because the added circuitry required to access the redundant memory schemes becomes excessive as the devices become larger.
Another way to overcome defects is through discretionary wiring. Discretionary wiring follows testing of a wafer containing many small, similar semiconductor devices, or clusters of semiconductor devices, which are manufactured using traditional batch processing methods up to but excluding the metal interconnect levels, and identifying the good and bad elements. Only good elements are interconnected by discretionary wiring to complete the structure. Texas Instruments, Inc. demonstrated the concept of discretionary wiring in the early 1960s. The Texas Instruments discretionary wiring method is discussed in a paper entitled "Wafer Scale Integration--Historical Perspective" by N. R. Strader and J. S. Kilby, published Sep. 20 and 21, 1984 in "Preprints for The SRC Workshop on Wafer Scale Integration" by Cooperative Research Semiconductor Research Corporation, P.O. Box 12053, Research Triangle Park, N.C., 27709. Texas Instruments created a map of good and bad elements on a wafer. For each wafer, a set of masks for metal and via interconnect patterns were then created to interconnect all the good elements into a single functional integrated circuit. The costs of testing and creating the unique masks made this approach not cost effective.
Many other companies have worked on wafer-size integrated circuits using a multiplicity of approaches to avoid defects in the resulting circuits. Most of the work has been done in the area of logic circuits, but some of the more recent work has been done in the field of integrated circuit memories.
Two recent well known efforts in wafer-size integrated circuit memories have been made by Inova Microelectronics Corp. and Anamartic, Ltd. In the Inova method described in U.S. Pat. No. 4,703,436, conventional single chip static RAMs are completely manufactured up to and including additional interconnect levels which define a bus that connects all chips together through fuses. All chips are tested and the bad chips are disconnected from the bus by blowing the fuses that connect the bad chips to the bus. The bus structure has redundant lines which are electrically connected by blowing fuses in a circuit-select decoder. The circuit select decoder, fuses, and test pads all represent overhead circuitry which must be provided in addition to the overhead circuitry present on the individual single chip memories, thereby reducing the overall memory density to less than what is available with conventional single chips. The Inova method addresses the chip enable input pins of the individual chips to be connected by applying additional address bits to the circuit select decoder on one chip of the wafer to extend the range of the addressing available on the individual chips and to reorganize the functionality of the wafer level memory in order to map around defects.
The Inova method does not work with chips having no chip select input. Most Dynamic Random Access Memories (DRAMs) have no chip select input. Therefore, the Inova method will not work with most DRAMs since it has no capability to provide for efficient refreshing of DRAMs. Additionally, the Inova method is limited to a single address port, and inserts detrimental fuse resistance in series with the power supply and ground lines. Further, certain failures in elements initially connected through fuses will produce failure of the remainder of the device before the fuses can be blown. The Inova patent does not address the effect of long metal buses on memory performance, nor does it address manufacturing memory products comprised of whole wafers.
Anamartic, a commercial wafer scale memory company in England, builds whole wafer memory circuits by connecting into long serial looping chains good clusters of DRAM memory cells contained on conventional DRAM chips. The wafer is totally manufactured through all levels. The final wafer level memory software is configured by repetitively accessing the serial chain to test for good and bad memory cells one at a time and substituting good cells for bad cells through the control logic (using software) until a continuously good serial shift register loop is created. The addresses of the good memory bits are stored in an EEPROM on a separate chip. When manufactured using DRAM technology, the serial memory organization eliminates conventional methods for refreshing the dynamic memory cells. Therefore, the wafer level memory must be continuously clocked to refresh the memory states. This increases the overall power dissipation of the wafer while making the average access time very slow (though still faster than magnetic disk storage devices). The control logic associated with each memory chip increases the support overhead on the wafer by at least 10% and severely limits the memory density per wafer. The off-wafer EEPROM chip prevents the Anamartic technology from providing a fully self supported wafer-level memory. Additionally, the software for addressing only good memory makes the device slow in operation.
DRAM memories must be refreshed (rewritten) periodically (approximately every 16 milliseconds for a 4 Mbit DRAM) and are notorious for high transient switching currents during addressing and refresh. Usually they contain no chip select input and are addressed by presenting a row and column address rather than a single address field for either an entire row or an entire column. For the construction of a conventional wafer-size DRAM memory, high current requirements and space for chip select and other addressing overhead must be accommodated.
A prior art conventional single chip integrated circuit memory is usually composed of a multiplicity of identical smaller memory blocks each of which contains memory cells, decode circuitry to decode an address to access an individual memory cell, sense amplifiers to sense (read) the state of the memory cell addressed, and line buffer drivers to drive local metal interconnect buses. Each single chip integrated circuit memory also contains other circuitry to perform control and timing functions, other required overhead circuitry to support the multiplicity of memory groups, and bond pads which are used to create a physical electrical connection to a package or other off-chip electrical contact. For combining multiple chips into a single memory, these overhead circuits or structures must support and/or control the group of smaller memory blocks as one common unit. Typically this prior art overhead circuitry may account for 50% of the total wafer area.